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Verification and Validation

NeST provides the right solution for complete outsourcing of design verification and supplements in-house verification efforts. We offer a complete verification solution to our customers ranging from HDL, HVL Block level Modeling & Simulation and Concept to Product level Testing/ Verification/ Validation.

Comprehensive expertise with several advanced verification methodologies:

  • Functional Verification
  • H/W S/W Co-Verification
  • Synthesizable Test Logic
  • Assertion based Verification
  • Formal Verification
  • Code Coverage Analysis
  • Bus Functional Modeling
  • Full Chip Verification
  • HVL (VERA, Specman)-based verification
  • C++ and Testbuilder-based verification
  • C-based verification (processor program and model)
  • Assembly Language-based verification (for processor sub-systems)

 

Our validation services include:

  • Macrocell Level / Chip level Validation
  • Diagnostic software, firmware-level testing
  • Reference design and prototyping
  • Debug using high end test and measurement equipment
  • Test Automation for testing  ICs in volumes